In modern electronic circuits, such as, for example, input/output (IO) buffers, it is desirable to control the variation of output impedance of the IO buffers for a variety of reasons, including, but not limited to, transmission line matching, minimizing switching noise (e.g., di/dt), optimizing signal swing, etc. In many high-speed applications, such as, for example, memory interfacing, it is important that the buffer output impedance closely matches the impedance of a circuit board to which the buffer is connected in order to reduce signal degradation. Tight control of output impedance is also required to reduce ground bounce.
In order to achieve such tight control of output impedance, a buffer, often referred to as a compensated buffer, is typically employed which is adapted to compensate for variations in process, supply voltage and/or temperature (PVT) conditions to which the buffer may be subjected. In one implementation, a PVT compensated buffer utilizes a PVT control block which monitors the variation of a block of one or more reference devices matched to corresponding devices (pre-drivers) in an output stage of the buffer to be compensated. The PVT control block generates a set of digital bits (PVTBITS) that are used to control the reference devices (e.g., turning the devices on or off) so as to maintain a constant output impedance. The output impedance of the reference block will be a function of the number of devices in the block that are turned on or off at any given time. These bits are also fed to the buffer to control the output impedance of the buffer output stage devices in a similar manner. The number of pre-drivers in the buffer output stage is directly proportional to the number of digital control bits.
Various IO standards, such as, for example, stub series terminated logic (SSTL), high-speed transceiver logic (HSTL), etc., specify the output impedance and/or output current of a receiver at specific values of output voltage (e.g., Vol or Voh) in order to ensure that there is sufficient margin for the receiver to function properly. Depending on certain requirements, SSTL and HSTL buffers can operate either in Class-I mode or in Class-II mode. In Class-I mode, an output drive strength of the buffer is such that the output impedance is twice that of the buffer operating in Class-II mode. While it would be advantageous to have a single buffer capable of operating in either Class-I or Class-II mode, standard buffer designs have, thus far, not be able to achieve this in an area efficient manner.
In a first known approach for implementing a buffer capable of operating in either Class-I or Class-II mode, two complete buffers, one buffer corresponding to Class-I output drive strength and a second buffer corresponding to Class-II output drive strength, are simply connected in parallel with one another. This approach, however, consumes significant silicon area and power and is therefore undesirable. In a second known approach, pre-drivers and output drivers used in a Class-I buffer are replicated twice in the same buffer; one set of pre-drivers and output drivers is turned on during Class-I operation and both sets are turned on during Class-II operation. This approach, however, still consumes substantial silicon area and is therefore not preferred.
Accordingly, there exists a need for an improved buffer circuit capable of operating in both Class-I and Class-II modes and that does not suffer from one or more of the problems exhibited by conventional buffer circuit designs.